Quantifies an Integrated Circuit’s Ability to Withstand Physical Attacks that Might Compromise Sensitive Information
This quantitative algorithm uses information about the layout of an integrated circuit to evaluate the circuit’s design for vulnerabilities to microprobing attacks. Microprobing is a type of physical attack on an integrated circuit that circumvents encryption and probes at signal wires to extract secure information. If successful, these attacks can compromise sensitive information such as personal data, encryption keys, and code format intellectual property. The most common reinforcement against microprobing attacks is active shielding, wherein meshes of trigger wires that surround the signal wires detect breaches and prevent the extraction of secure information. This protection has significant problems, however, as it requires additional routing layers that may be too costly or otherwise unavailable within the integrated circuit design. Additionally, certain designs of active shields are simply ineffective against microprobing attacks.
Researchers at the University of Florida have developed a framework for evaluating a microprobing prevention design based on an analysis of the circuit’s layout structure and its protection against known exploits. By quantifying the vulnerability to microprobing of an integrated circuit, the algorithm enables more effective development and management of anti-probing systems.
An algorithm to verify and assess microprobing vulnerabilities on integrated circuits
- Evaluates the vulnerability of an integrated circuit to a microprobing attack, enabling the development of more efficient and accurate anti-probing protections
- Quantifies an existing microprobing prevention system’s level of security, allowing for easy management and analysis among ranges of security system layouts
- Identifies parts of the integrated circuit that are more or less vulnerable, permitting the cost-saving reallocation of active shielding to ensure a maximal level of security
This algorithm quantifies the vulnerability of integrated circuits to microprobing attacks by using information drawn from the circuit’s layout. The algorithm uses the nets of signaling pathways that are likely targets for a microprobing attack to analyze the layout of the integrated circuit, determining the areas that are not sufficiently protected from potential attacks. This framework for identifying the vulnerabilities of integrated circuits, establishes a quantitative relationship between different assessed layouts, enabling designers to develop anti-probing hardware arrangements with better resistances to security breaches.